The present invention relates to arbitration in computer systems. More particularly the invention is directed to an arbitration system and method based on a dual rotative and weighted priority scheme for arbitrating access of shared resources to a common bus.
In high speed telecommunication networks wherein a plurality of resources share a common bus, arbitration of the requests to access the bus is a critical operation that must insure fairness and be accomplished in a minimum time cycle. Mainly two types of arbiters have been implemented to reach both or either one of these goals. In a first type, which is generally called a linear arbitration, a fixed priority value is associated to each resource and the highest priority requester may prevent access to the bus by the lower priority requesters until it has relinquished control of the bus. This technique suffers the drawback of being unfair. The other general type of arbitration system allows that each requesting device may gain access to the bus in an equitable manner. Several circuit architectures allow this fairness priority arbitration. In the round robin design, the arbiter scans through the input devices as long as an active requester is reached. The time arbitration increases directly with the number of input devices. Moreover, once an active requester is reached, a weighted priority value is computed for it and thus the fairness of the arbitration depends on the design of the priority algorithm. In case of a high number of input devices, the circuits implementation of the priority algorithm is of a large scale.
U.S. Pat. No. 5,519,837 describes a pseudo-round-robin arbiter comprising a multiplicity of arbiter cells for arbitrating among a plurality of requests. The requests are combined in various groupings and simultaneously provided to all the cells which are organized as a multiple levels hierarchy. The outputs of the higher level cells serve as enablements to successively related lower level cells in progression by level. The arbiter cells also receive inputs from respective token lines to initiate control of the grant signals. This type of hierarchical grouping allows that the time delay attributed to arbitrating requests grows logarithmically with the number of requesters; but, on the other hand, the arbitration priority is given to the group which is preliminarily selected by the token bit over the other groups, thereby leading to a less fair design than a flat arbitration scheme, wherein each input request is processed with the same priority value.
Therefore, the present invention is directed towards solving the aforementioned problems. Accordingly, it would be desirable to be able to provide a fair, compact and high speed arbiter.
It is an object of this invention to provide a fair and high speed arbitration circuit for use in connection with based bus systems.
It is another object of the invention to provide such arbiter operating with a fixed priority scheme.
Still further, it is an object of the invention to provide a method for arbitrating access of a plurality of resources to a common bus.
According to the present invention, a mixed rotative and weighted arbiter is provided. The arbiter is composed of a token circuit which delivers a token vector having one position set active. The token vector as well as a plurality of request signals supplied by requesting devices are input to a rotative arbitration circuit. The rotative arbitration circuit processes a round robin algorithm to output a rotative request vector having input requests ordered from a higher to a lower priority configuration according to the active position of the token vector. The arbiter further comprises a weighted arbitration circuit connected to the output of the rotative arbitration circuit for generating a weighted request vector determining a linear priority configuration of the rotative request vector. A grant generation circuit is connected to the output of the weighted arbitration circuit and to the output of the token circuit to deliver a grant order to the device which may gain access to the bus and a plurality of no grant orders to the others devices.
In the preferred implementation, a token confirm vector is generated simultaneously to the grant order. The token confirm vector which represents the grant/no grant orders configuration is sent to the token circuit to update the content of the cells. The active position which may be the same or a different one than for the previous token vector is shifted to the next position in order to change the priority for the next arbitration cycle.